1. Field of the Invention
The invention relates to integrated circuits, and more particularly, to a wafer structure that allows at least a bonding pad formed on an IC chip to be firmly secured to the IC chip so that it will not become detached during assembly of the IC package. Furthermore, the invention relates to a method for forming such a wafer structure.
2. Description of the Related Art
As new IC technology allows higher and higher packing density of semiconductor devices on a single IC chip, the bonding pads that are provided on the IC chip are also made smaller and smaller. Bonding pads are made of conductive material, such as an alloy of aluminum and copper, for electrically connecting semiconductor devices in the IC chip to external pins on the IC package. A drawback of conventionally formed bonding pads is that they are readily detached or stripped from the IC chip during assembly of the IC chip package; this is particularly evident using the chip-on-board method of IC assembly. This significantly decreases the assembly yield of good IC packages.
A conventional method for forming at least a bonding pad on an IC chip, which would be easily detached from the IC chip is illustrated in FIG. 1A through FIG. 1G.
Referring first to FIG. 1A, a stage in the fabrication process for the IC chip is shown which includes a silicon substrate 10 on which a field oxide layer 20 defining the active region is formed. This active region part of the wafer is hereinafter also referred to as the "active area". Further, at least one part of the wafer, which is hereinafter referred to as the "pad area" as indicated by the numeral 25, is reserved for the formation of a bonding pad thereon. Impurities are diffused into the active area so as to adjust the threshold voltage thereof. Further, a gate oxide layer 30 and a polysilicon gate layer 40 are successively formed on the active area to constitute a gate. Using the gate (30, 40) as a mask, an ion implantation process is conducted on the wafer so as to diffuse an impurity, such as phosphor ions, into the silicon substrate 10, thereby forming a pair of lightly-doped source/drain regions 11 in the wafer.
Referring next to FIG. 1B, in the subsequent step, spacer walls 12 are formed on the sidewalls of the gate (30, 40). Referring further to FIG. 1C, using the spacer walls 12 as a mask, an ion implantation process is conducted on the wafer so as to diffuse an impurity, such as arsenic ions, into the silicon substrate 10. As a result, a pair of heavily doped source/drain regions 13 are formed in the wafer. Up to this point, the pad area 25 includes the field oxide layer 20 on the silicon substrate 10.
Referring further to FIG. 1D, in the subsequent step, a layer of borophosphosilicate glass (BPSG) 50 is deposited over the entire wafer. Anisotropic dry etching is then conducted on the wafer with a predefined mask for removal of selected parts of the BPSG layer 50, thereby forming a plurality of metal contact openings 14 through the BPSG layer 50.
Referring next to FIG. 1E, in the subsequent step, sputtering deposition and rapid thermal processing (RTP) are conducted on the wafer so as to form a layer of titanic compound 60 (which is a composition of titanium nitride and titanium silicide (TiN/TiSi.sub.2)), over the surface of the silicon substrate 10, and to form a layer of a composition of titanium nitride and titanium silicide oxide (TiN/TiSi.sub.x O.sub.y) over the surface of the BPSG layer 50.
Referring to FIG. 1F, in the subsequent step, the chemical-vapor deposition (CVD) method is used to deposit a layer of tungsten 70 over the titanic compound layer 60. Dry etching is then conducted on the wafer using the titanic compound layer 60 as an etch end point so as to planarize the surface of the titanic compound layer 60 and the tungsten layer 70. Sputtering deposition is then conducted on the wafer so as to form a metallization layer 80 of, for example, aluminum over the wafer. The foregoing steps also allow the BPSG layer 50, the titanic compound layer 60, and the metallization layer 80 to be formed in the pad area 25.
Referring next to FIG. 1G, in the subsequent step, a mask and photolithographic process is conducted on the metallization layer 80 so as to define a plurality of connecting wires for the IC chip. A passivation layer 90 is then deposited over the wafer for protecting the IC chip. After that, an etch process with a predefined mask is conducted on the pad area 25 for removal of at least a selected part of the passivation layer 90. As a result of this process, an opening 91 is formed through the passivation layer 90 so as to expose the underlying metallization layer 80, thus allowing the metallization layer 80 to serve as a bonding pad that can electrically connect the IC chip to external pins. During assembly of the IC package (particularly by the chip-on-board method), the metallization layer 80 which serves as a bonding pad formed in the pad area 25 is easily detached from the encasing passivation layer 90, thus significantly affecting the assembly yield of good IC packages. There exists, therefore, a need for a new structure for the bonding pad which allows the bonding pad to be securely formed on the IC chip without being peeled away during assembly of the IC package.